The present invention relates to communications networks and, more particularly, to controlling bit slippage in high-speed communications systems.
Large communications networks, e.g., digital telecommunication switching networks, typically require extremely accurate clocking systems to synchronize the various time related operations performed in such communications networks. Typically, the clocking signals in these networks originate from a centralized clocking source that generates and transmits clocking signals throughout the network. Although such clocking schemes are satisfactory for most applications, they do suffer from a number of drawbacks. In particular, the reliance on a centralized clocking source leaves a distributed processing system susceptible to system-wide failures in the event of a malfunction in the clocking center. The dependence upon a single centralized clock may be minimized by utilizing a set of redundant clock sources. In such a system, there is a centralized clock center having a set of clocks that generate and transmit a group of redundant clock signals throughout the network.
For example, in well-known synchronous, time-division multiplexed data transmission systems, each device across the a transmission link has a local clock source for the timing of operations at that device. At the transmitter device, the local clock generates bit and framing pulses to align the outgoing bits in appropriate time slots, assembles frames of data, and controls the insertion of framing bits or signals which delineate successive frames. At the receiving device, the local clock of this device generates bit and framing pulses that disassemble the incoming frames and recover the transmitted bits in each of the time slots. As is well-known, transmission links, such as a cable or optical fiber, have propagation delays which create certain timing misalignments during data transmission. Further, as is well-known, clock sources (local or common) produce so-called xe2x80x9ctiming jittersxe2x80x9d (also referred to in the art as xe2x80x9cphase noisexe2x80x9d, xe2x80x9ctiming errorsxe2x80x9d, or xe2x80x9cwrong-slot errorsxe2x80x9d) that cause misalignment of data bits, i.e., xe2x80x9cbit slippagexe2x80x9d, in reference to certain timing markers, i.e., frames.
In low speed synchronous digital links, the timing jitters introduced from a clock source are relatively small as compared to the total period of a bit interval. Thus, the effect of the time jitter, e.g., bit slippage, can be eliminated by using a well-known phase-locked loop circuit that resides in a clock recovery circuit. However, in high-speed synchronous digital links, e.g., multi-gigabit fiberoptic links, timing jitters are caused from a variety of well-known sources (e.g., clock source imperfection, phase noise from phase-locked loops, etc.) and such timing jitters are large as compared to the total period of a bit interval. Thus, it is not uncommon in such high-speed links to incur timing jitters on the order of several bit intervals. In such cases, the phase-lock loop solution used in low speed applications will fail to follow and track the change resulting in cycles slips. These cycle slips, in turn, cause the transmitted and received data bits across the high-speed link to be misaligned with framing markers, i.e., bit slippage has occurred.
The art is replete with a variety of techniques to control bit slips. For example, U.S. Pat. No. 3,887,769 issued to M. P. Cichetti, Jr. et al. on Jun. 3, 1975, hereby incorporated herein by reference for all purposes, describes a technique which employs an elastic data bit store for frame synchronization. More particularly, this scheme utilizes a elastic data bit store to introduce a variable delay in the incoming data stream to allow a so-called frame find circuit to detect a time-shifted framing code thereby reducing bit slippage. Further, U.S. Pat. No. 4,744,081 issued to K. M. Buckland on May 10, 1998, hereby incorporated herein by reference for all purposes, describes a particular frame find circuit design in which a continuous bit slip of data words in a serial data stream are monitored for the presence of the frame word. In accordance with this scheme, all possible bit orientations are examined in a single frame until the frame word is found. Also, U.S. Pat. No. 5,577,075 issued to J. M. Cotton et al. on Nov. 19, 1996, hereby incorporated herein by reference for all purposes, describes a bit slippage technique employing a 12-bit detection window to detect a 10-bit synchronization code. Cotton""s technique provides for xc2x11 bit slip detection and can be generalized to detect any m-bit pattern in a (m+n) bit window, where m and n are integers.
Although such prior art bit slippage schemes provide reasonable solutions to the mitigating effects of bit slippage, such schemes do not address bit slippage in a two-way high-speed communications link. That is, in these prior bit slippage schemes, the task of controlling bit slippage is entirely performed on the receiver side of the communication to the exclusion of the transmission side. Thus, in two-way high-speed communication links, even though there exists the capacity to engage the transmission side in bit slippage control such receiver-centric solutions do not engage the transmission side in the control of bit slips. Furthermore, in two-way high-speed communications systems employing elastic data bit stores, bit slips can occur at a very high rate at the receiver. As such, in order to mitigate communications errors such as frame markers slipping out of the elastic stores, the receiver-centric approaches of the prior art require the use of very large elastic stores. Since the size and complexity of the supporting bit slip circuitry is proportional to the size of the elastic store, the implementation of such communications systems becomes more complex and expensive in terms of hardware requirements.
Therefore, a need exists for improving bit slip control in a high-speed, two-way, communications link.
The present invention provides a method and apparatus for controlling bit slips in a high-speed, two-way, communications link. More particularly, in accordance with the invention, the entire communications link, comprising, inter alia, a receiver, a transmitter and the physical communications channel is operated as a feedback loop. That is, in accordance with the invention, the detection of bit slips is performed continuously in the receiver and a bit slip signal is generated that indicates the number of bit slips and the direction, i.e., forward or backward, of the bit slip. In accordance with the preferred embodiment of the invention, the bit-slip signal is communicated to the transmitter and certain actions are performed to introduce bit adjustments in the bit stream to eliminate the effects of any future bit slips. In accordance with the preferred embodiment of the invention, the bit slip signal contains an indication of the number of bit slips which have occurred, the time between bit slips, and the direction of the slip. As a function of this information from the bit slip signal, bit adjustments are made in the communications stream to correct for the bit slips and mitigate any effect in future transmission. For example, such bit adjustments include adding bits to particular data words in the bit stream or repositioning pointers used to traverse the data stream. Advantageously, in accordance with the invention, both the receiver and transmitter are actively engaged in controlling bit slippage across the communications link thereby improving the robustness and efficiency of the communications exchange.